1. Field of the Invention
The embodiments of the invention generally relate to field effect transistors, and, more particularly, to a low-capacitance contact for long gate-length planar and non-planar devices with small contacted pitch.
2. Description of the Related Art
Despite current lithography techniques which allow devices to be formed with reduced dimensions, the scaling of complementary metal oxide semiconductor (CMOS) devices and particularly, the scaling of CMOS transistor gate lengths is limited by leakage power. Logic circuit density is limited by the contacted pitch of field effect transistors (i.e., the minimum metal line width spacing plus addition for via or contact covers or landing pads) and this contacted pitch is in turn limited by the (non-shrinking) gate lengths of the transistors. It would be advantageous over the prior art to provide a transistor structure that can simultaneously minimize leakage power, minimize parasitic capacitance between the source/drain contacts and the gate electrode and optimize device density.